This invention relates to debugging the operation of integrated circuits such as programmable integrated circuits with hardwired circuitry such as system-on-chip circuitry.
Programmable integrated circuits such as field programmable gate arrays (FPGAs) contain logic circuitry that can be programmed by a user to perform custom functions. System-on-chip (SOC) integrated circuits include microprocessor circuitry, memory, interconnect buses, and peripherals. Some integrated circuits include a first portion that is based on programmable logic circuitry of the type found in many field programmable gate array circuits and a second portion that is based on hardwired system-on-chip circuitry. These integrated circuits, which are sometimes referred to as system-on-chip field-programmable gate arrays (SOC FPGAs), exhibit flexibility due to the presence of programmable circuitry and substantial processing power due to the presence of hardwired system-on-chip circuitry.
Debugging schemes for some system-on-chip integrated circuits are invasive and require halting of the processing circuitry. Existing non-invasive debugging schemes do not require that the processing circuitry be halted during debugging, but only allow access to limited performance monitoring information and instruction tracing.
It would therefore be desirable to be able to perform improved debugging operations on integrated circuits with processors and memory.